Hybrid bonding

CXMT

2026-10-16 12:28:22

CXMT’s DRAM 4F² and vertical transistor push raises questions for memory leaders

Changxin Memory Technologies, or CXMT, said it has made major progress in DRAM devices, 4F² cell architecture and hybrid bonding, a set of developments that quickly shifted investor attention to the global memory market. The concern outlined in the source report is straightforward: if a Chinese DRAM maker can break through a core technology barrier and pair that with a structure that lifts bit output per wafer, effective supply could rise faster than many had expected. The report focuses on two changes. One is the move from the mainstream 6F² cell layout to 4F². The other is CXMT’s self-developed VSG, short for Vertical Surrounded Gate, a vertical gate-all-around style transistor that supports that layout. Under the same process node, a 4F² cell is described as roughly one-third smaller than a 6F² cell, which in theory allows about 50% more memory cells in the same area, though chip-level gains would be lower once peripheral circuits are included. The analysis then walks through how a DRAM 1T1C cell works, why vertical transistors matter, where 4F² manufacturing becomes difficult, and how the timetable at Samsung, SK hynix and Micron compares with CXMT’s announcement. The source argues that near-term industry fundamentals may not change much, but the medium-term supply outlook after 2028 could look different if 4F² reaches production and yields scale.

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ASML

2026-10-16 00:19:13

SemiAnalysis says ASML appears to be developing chip-to-wafer hybrid bonding tools

SemiAnalysis said in an Oct. 15 article that ASML has not formally announced a hybrid bonding product, but patents, prior media reports and the company’s roadmap all point to ongoing development in the segment. The article argued that ASML may first introduce a more technically demanding chip-to-wafer hybrid bonding tool, framing the move as an extension of vertical integration. Patent filings describe a system that runs on a track, with each chip placed in an individual carrier and moved through inspection, cleaning, plasma activation, topography inspection, leveling, coarse alignment, position correction and fine alignment before entering the bonding station. The piece also noted that the system’s repeatability is about 10 microns, far short of the roughly 50 nanometers required for bonding. ASML filed 27 bonding patent families between December 2022 and November 2024, most of them aimed at chip-to-wafer applications. The Elec reported in March that ASML had begun hybrid bonding machine architecture design work with Prodrive Technologies and VDL ETG.

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SemiAnalysis

2026-10-12 03:30:43

SemiAnalysis stays bearish on HBM hybrid bonding as lower-stack designs weaken the case for D2W

SemiAnalysis said memory suppliers are starting to acknowledge the idea of HBM "de-spec," and the research firm is keeping its bearish view on D2W hybrid bonding for HBM. Its argument is straightforward: the main value of hybrid bonding in HBM is to solve package height limits created by very tall stacks, and that issue becomes much less pressing if the market shifts toward 4-hi or 8-hi products. The firm also pointed to SK hynix, which has publicly said 16-hi HBM is difficult to manufacture, while market priorities are moving from capacity toward bandwidth. That view is not universally shared. Jukan, a researcher at Citrini, cited Daishin Securities in South Korea as saying mass-production discussions around lower-stack HBM such as 4-high and 6-high have effectively been canceled, and plans to move from 12-high to 8-high have also been reduced. Bank of America offered a different read as well, saying some chipmakers could supply 8-hi HBM4 for Rubin GPUs next year and arguing that such de-spec could act as a growth catalyst for memory rather than a negative. Even so, BofA said it has not yet seen meaningful wafer input for 8-hi HBM4 and expects shipment volumes to remain small through the first half of 2027, and possibly until the third quarter.

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Samsung Elect

2026-10-10 02:07:12

Samsung hybrid-bonded HBM sample report draws attention, while SK hynix keeps advancing its current packaging path

Competition in next-generation high-bandwidth memory, or HBM, is increasingly centered on advanced packaging rather than DRAM performance alone. A report cited by Damnang on Oct. 7, based on interviews with technical personnel, said SK hynix has run into difficulties developing hybrid bonding for future HBM, while Samsung Electronics has reportedly begun delivering samples using the technology to customers. The report did not identify the HBM generation, stack height, or customers involved, and it was not based on official statements from either company, leaving the actual development gap unclear. At the same time, SK hynix has continued to move forward with its existing packaging route. On June 18, the company said it had delivered 12-layer, 48GB HBM4E samples to major customers using its Advanced MR-MUF packaging technology, adding that thermal resistance improved by 17% versus HBM4. Samsung, for its part, introduced its hybrid copper bonding technology, HCB, on March 17 in materials tied to GTC-related events, saying the approach could cut thermal resistance by more than 20% compared with thermocompression bonding. The central issue is no longer whether hybrid bonding works in a lab. The harder questions involve process stability, yield, cost, throughput, and customer qualification. Those factors, rather than sample delivery alone, will determine whether an early technical lead can become a durable commercial advantage.

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Ableprint

2026-10-02 00:41:26

Ableprint to invest NT$300 million in Saultech private placement for a 16.67% stake

Ableprint Technology said on Oct. 1 that it will invest NT$300 million in Saultech Technology through a private placement, subscribing to 6 million common shares at NT$50 each. Once the deal closes, Ableprint will hold a 16.67% stake in Saultech. The company described the transaction as a strategic investment aimed at building a long-term alliance in semiconductor equipment and strengthening technology integration and market expansion. The tie-up centers on complementary capabilities in advanced packaging. Saultech brings high-precision Pick & Place technology, with die bonder equipment focused on front-end die placement, while Ableprint specializes in back-end debubbling and high-pressure lamination equipment. The companies expect the upstream and downstream integration to support more complete solutions for customers. According to the report, the NT$300 million investment has a limited impact on Ableprint’s finances. Based on recent financial statements, the amount accounts for 3.47% of total assets and 4.48% of equity attributable to owners of the parent. Ableprint also has about NT$6.058 billion in working capital.

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3D DRAM

2026-09-14 11:09:11

3D DRAM race heats up as AMD, NAURA and memory giants push new architectures and process tools

Two developments in the first week of September 2026 put 3D DRAM back at the center of the memory industry. AMD disclosed internal test results for a Hybrid Bonding-based 3D DRAM architecture, saying energy efficiency could improve by as much as 17x versus conventional HBM stacks. Around the same time, Chinese semiconductor equipment maker NAURA published an IEEE paper describing a manufacturing advance for next-generation 3D DRAM, including a two-step cyclic etch process for 64-layer alternating silicon and silicon-germanium structures, structural uniformity above 95%, an etch selectivity above 500:1, and silicon loss below 10 angstroms in a 200 nm interlayer structure. The report argues that these announcements matter because conventional DRAM scaling is nearing physical and economic limits. It also reviews the two main technical paths now being pursued, 4F2 VCT and VS-CAT, and outlines how Samsung Electronics, SK hynix, and Micron are positioning themselves. Beyond chipmakers, the shift is also reshaping the equipment chain, from high-aspect-ratio etch to atomic layer deposition, wafer bonding, CMP, cleaning, inspection, coating and developing, testing, and high-purity process systems.

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TSMC

2026-09-02 06:56:05

TSMC Sticks With Microbumps for HBM Packaging; 5μm-Class Output Seen in 2H 2028

TSMC expects to keep using conventional microbumps, not hybrid bonding, to link high-bandwidth memory with AI accelerators in advanced packaging over the near term, according to materials industry sources on Sept. 2. Finer-pitch microbumps are likely to remain in use through late HBM4 and into early HBM5, reflecting material development lead times. TSMC has asked materials and equipment partners to develop bonding and underfill solutions for roughly 5μm bumps, and Korean and Japanese suppliers have started work. Volume production for 5μm-class bumps is expected in the second half of 2028. Today's HBM3E bumps are about 15–25μm high, while HBM4 is approaching around 10μm. Japanese materials suppliers have said it is difficult to guarantee quality below 15μm. The push for shorter, finer bumps comes from height limits on HBM stacks and the need for denser interconnects. JEDEC caps HBM stack height at 775μm. In TSMC's CoWoS flow, GPU dies and preassembled HBM stacks attach to a silicon interposer via microbumps, while SK hynix and Samsung Electronics build the 16-layer DRAM die stacks in HBM packages. First- and second-generation HBM relied on larger solder bumps; microbumps became mainstream around the HBM3 generation. SK hynix uses MR-MUF, and Samsung Electronics uses TC-NCF. Hybrid bonding can make interconnects thinner and denser by directly bonding copper pads, and TSMC has applied it to logic stacking on its SoIC platform, but HBM still connects to the interposer through microbumps.

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SK Hynix

2026-08-24 01:16:47

SK Hynix brings advanced packaging, including Intel EMIB, into next-generation HBM plan

SK Hynix is bringing advanced packaging technologies into its next-generation high-bandwidth memory, or HBM, roadmap, including Intel’s Embedded Multi-die Interconnect Bridge, better known as EMIB. The company also said it ultimately plans to move into the 3D packaging era as it pushes its memory stack design further. At the 2026 Hot Chips conference, Jaesik Lee, vice president of package engineering at SK Hynix, presented a session titled "Advanced Packaging for High-Bandwidth Memory." In that presentation, he detailed how the company intends to use packaging advances to speed up its HBM product roadmap. SK Hynix is currently exploring methods such as hybrid bonding to break past the 16-layer stacking limit. Looking ahead, the company also plans to address power consumption challenges by increasing the number of through-silicon vias, improving IO speed for logic process integration, and optimizing the power delivery network, or PDN. As of publication, SK Hynix shares in South Korea were up 1.71%.

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